The present invention relates to an electrostatic discharge (ESD) cell and, more particularly, to an ESD cell applicable to multiple-power-input and mixed-voltage integrated circuits (ICs) and capable of maintaining power sequence independence of each power supply.
The technique of ESD cell is well known to those of ordinary skill in the art. For instance, in a conventional method of providing ESD protection, a circuit is provided in the device to guide ESD of potential danger to a ground end, and is kept away from operating devices in the circuit during ESD event.
Generally speaking, a power source required by a chip is separately provided to avoid noise coupling between bus pins thereof. However, this way of providing a separate power source will cause the problem of ESD. As shown in FIG. 1, a power source Vcco of an I/O pin 10 is separated from a power source Vccl connected to an internal circuit 12, and a GND bus thereof is also separated. A resistance Rsub exists between a ground end of pin, Vsso, and a ground end of internal circuit, Vssi. When an ESD pulse is inputted to the pin 10, the pulse current will be discharged via a path 1 shown in the figure with respect to the ground end Vssi, and this path 1 is the preferable discharge path. However, the resistance of the resistor Rsub between the ground end Vssi and the ground end Vsso may be too large so that a too large voltage drop is generated between the two ground ends when the pulse current flows through, resulting in a too large voltage difference between the pin 10 and the Vssi. If this voltage difference is too large, a path 2 shown in FIG. 1 will start being conducted to perform ESD, hence damaging some devices of the internal circuit 12 due to high voltage discharge.
On the other hand, if there is an ESD cell 16 between the power sources Vcci and Vcco, as shown in FIG. 2, the ESD current will easily flow through a diode D1 and the ESD cell 16 and then reach the power source Vccl, triggering a ESD power clamp 14 between the power source Vccl and the ground end Vssi, as a path 3 shown in the figure. Additionally, if there is another ESD cell 18 connected between the ground ends Vsso and Vssi, the ESD current will more efficiently flow out from the ground end Vssi via a path 4 shown in the figure. The internal circuit 12 thus will not be overloaded by the ESD current and is protected by the ESD cells 16 and 18. Therefore, ESD cells between different input power sources are very important to protect the internal circuit.
In the prior art, back-to-back diodes or diode-connected devices are usually used as an ESD cell for providing the above function. As shown in FIGS. 3 and 4, the number of diodes in these two kinds of ESD cells depends on the requirement of noise resistance or the voltage difference between different power sources at two ends of the circuit. As shown in FIG. 3, if the voltages of a rated power source Vcc1 and a power source Vcc2 are the same and the power source Vcc1 endures higher noise, the number of diodes from the power source Vcc1 to the power source Vcc2 needs to relatively increase to enhance the capability of noise resistance. However, the increase of the number of diodes will relatively reduce the protection benefit of this ESD cell. As shown in FIG. 4, if the voltage of the power source Vcc1 is larger than that of the power source Vcc2, diode-connected dervices between them needs to generate a voltage difference from the power source Vcc1 to the power source Vcc2 larger than the voltage difference between the two power sources to compensate the voltage difference in between, thereby avoiding undesirable load effect between the two power sources.
Exactly as said above, in order to avoid noise interference between pins of different power sources, a considerable number of diodes are used in the above ESD cells, relatively reducing the benefit of the cells. Additionally, these kinds of ESD modules will let power sources at two ends have a sequentially dependent characteristic, which has potential problems in circuit design. Moreover, because the functions of present ICs tend to be diversified, many different power sources are required to provide a separate power source for each individual internal circuit. In order to save power dissipation, each individual internal circuit can be independently activated or deactivated according to dynamic operational requirement. Such a sequential characteristic of power supply will easily cause problems in circuit design when using the above back-to-back diodes type ESD cell.
As shown in FIG. 2, in a power-saving mode, if the power source Vccl is deactivated, electric energy supplied by the power source Vcco will flow to the deactivated power source Vcci via the ESD cell, letting the power source Vccl start providing electric energy undesirably. Therefore, if the sequence of power supply between different power sources is improperly designed, the object of power saving cannot be achieved, and the situation of short circuit will also arise due to injection of current.
Accordingly, using back-to-back diodes or diode-connected devices as an ESD cell in the prior art has problems when the voltages of power sources are different, and has the problem of noise interference when the voltages thereof are the same. Moreover, the requirement of sequence independence of power sources cannot be met. In other words, when two power input pins of a chip require two different voltages, or the degrees of noise endurance are different, the number of diodes of the module needs to be modified, reducing the benefit of this ESD cell. In consideration of these problems, the present invention proposes an ESD cell applicable to multiple input sides of power sources so that current will not be drained from an activated input power source to a deactivated input power source no matter what the sequence of the input power sources is.
In consideration of the above problems in the prior art ESD cell, the primary object of the present invention is to provide an ESD cell applicable to multiple-power-input and mixed-voltage ICs and capable of maintaining power sequence independence of each power source, thereby achieving the object of whole chip protection.
Another object of the present invention is to provide an ESD cell to effectively isolate noise interference at two ends of a power supply and not to reduce its benefit of ESD protection, hence effectively resolving the drawbacks of the prior art ESD cell.
To achieve the above objects, an ESD cell of the present invention is formed of a voltage selector circuit, a RC circuit, and an N-type metal oxide semiconductor (NMOS). Two separate power source pins connected to the NMOS can conduct the channel thereof to connect the two separate power sources to lead out the ESD current along a designed path when enduring an ESD pulse, hence avoiding damage to internal circuits. The channel of the NMOS is conducted and keeps open circuit to really isolate the two power sources under normal operation.
The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawings, in which: